Model-based Test Generation
                    
                                       
                       
The goal of this project is to generate tests that can be used to validate
           an implementation confirms to a specification. There are two approaches
         that  we are pursuing: one is automatic test generation from models
   written      in EFSM (Extend Finite State Machine) or hybrid systems,
and    another is   manual   test generation from RTSJ (Real-Time Specification
  of Java). For   the latter,   visit Test Suite
          for Realtime Java (created in 2001). 
                                           
  
                                           
For the model-based test generation, the goal is to automatically generate 
 a test suite that meets particular coverage criteria from specification 
       in  EFSM or hybrid systems. The approach to integrate random test-trace
       generator    with targeted test-trace generator based on model checking.
      We use model-checking    approaches to make test generation more flexible,
      efficient, and effective.  An enhanced model checker will work as a
generic test generator: it takes the coverage criteria encoded in some temporal
logic and the specification system as the input, and produces the test suite
achieving the coverage.  Essentially the combination
of the generic test generator and the criteria given as temporal properties
will function as a special test generator dedicated  for such   criteria.
This is done without having to  implement a different   test generator  
for each coverage criteria. The approach  also exploits  well-developed model-checking
    techniques to make test generation   more  efficient. Moreover, the richness
    of temporal properties allows us to  express both generic and system-specific
    coverage criteria.
                                           
  
                                           
The following figure described the overall approach to the test generation 
          from hybrid system models specified in CHARON. 
      
                                       
People
                                       
      
 External Collaborators
                         
                         
Former Members
  - Dr. Hyong S. Hong
- Dr. Na Young Lee 
- Dr. Li Tan
Activities
                        
On the theoretical side, we have shown that many traditional coverage
criteria can be encoded as w-CTL formulas [HLO02]. On the practical side,
we are implementing a preliminary version of randomized test generator for
CHARON. Our next step is to implement a counter-example guided test generator
 for CHARON.
                        
Publication
-  [TKSL04]
 Model-based Testing and Monitoring for Hybrid Embedded Systems,
  Li Tan, Jesung Kim, Oleg Sokolsky. and Insup Lee,
  IEEE Int. Conf. on Information Reuse and Integration (IEEE IRI-2004),
  Nov 8-10, 2004.
-  [TSL04]
 Specification-based Testing with Linear Temporal Logic,
  Li Tan, Oleg Sokolsky, and Insup Lee,
  IEEE Int. Conf. on Information Reuse and Integration (IEEE IRI-2004),
  Nov 8-10, 2004.
- [TKL03]
 Testing and Monitoring Model-based Generated Program, Li Tan, Jesung Kim, 
    and Insup Lee, in the third workshop on Runtime Verification (RV'03). Electronic 
    Notes in Theoretic Computer Science, Volume 89, No. 2. Elsevier Science. (Abstract 
    - Full Postscript 
    File - PDF File)
- [HC03]
 Data Flow Testing as Model Checking, Hyoung Seok Hong, Sung Deok §³ha, 
    Insup Lee, Oleg Sokolsky, and Hasan Ural, in the Proceedings of Internal 
    Conference on Software Engineering (ICSE'03), Portland, Oregon, May 3-10, 
    2003, (Abstract 
    - Full Postscript 
    File - PDF File)
-  [TSL03]
 Property-Coverage Testing. L. Tan, O. Sokolsky, and I. Lee. Technical Report 
    MS-CIS-03-02. January 2003. (Full 
    Postscript File - PDF 
    File)
-  [HLS02]
 A Temporal Logic Based Theory of Test Coverage and Generation, H. Hong, I. 
    Lee, O. Sokolsky, and H. Ural, International  Conference on Tools 
    and Algorithms for Construction and Analysis of Systems (TACAS2002), Grenoble, 
    France, April 8 - 11, 2002. (Abstract - Full 
    Postscript File - PDF 
    File)
- [HLLLS02]
 Testing the Electrical Throttle Control, Hyoung S. Hong, Insup Lee, Na Young 
    Lee, Martin Leucker, Oleg Sokolsky, Technical Report MS-CIS-02-11, April 2002. 
    (Full 
    Poscript File - PDF 
    File)
 
- [HLSC01] 
 Automatic Test Generation from Statecharts Using Model Checking, Hyoung Seok 
    Hong, Insup Lee, Oleg Sokolsky, Sung Deok Cha, Technical Report MS-CIS-01-07, 
    Feb 2001. (Full 
    Poscript File - PDF 
    File)
 
 
Links
                      
                      
Meetings
                      
            - Regular weekly meeting: 2:00-3:00
    pm  every Wednesday afternoon in Room 202 of Moore Building.
 
-                               Project meeting,
 9:00am-2:00 pm, 	      Monday, November 18, 2002, in Moore 202.